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PRELIMINARY DATA SHEET
SKY73134: Wideband PLL Frequency Synthesizer
Applications
Cellular base station systems: GSM/EDGE, CDMA2000, WCDMA, TD-SCDMA, LTE Other wireless communication systems
Description
The SKY73134 is a wideband integer-N frequency synthesizer with an approximately 6 GHz locking range. The device includes four differential Voltage Controlled Oscillators (VCOs), which cover the output frequency range from 2.8 GHz to 5.6 GHz. By applying internal VCO division by 1, 2, 3, 4, or 8, the output frequency range can be increased from 0.375 GHz to 5.6 GHz, monitored at the RF output. The direct, non-divided internal VCO frequency can also be monitored at the bidirectional VCO pins. The VCO selection can be automatic based on the target RF output. The flexible SKY74134 configuration allows the loop to be locked by an external VCO or external Phase Locked Loop (PLL), or the device can use the divider chain only. The SKY73134 is controlled by a bidirectional read/write serial to parallel interface. The SKY73134 frequency synthesizer is manufactured with a BiCMOS 0.18 m SiGe process and provided in a compact, 32-pin RF Land Grid Array (RFLGA). The pin configuration and package are shown in Figure 1. A functional block diagram is shown in Figure 2. Signal pin assignments and functional pin descriptions are provided in Table 1.
Features
Output frequency range: 0.375 to 5.6 GHz Integer-N frequency synthesizer Low phase noise VCO Four integrated VCOs with automatic digital frequency calibration Automatic VCO selection based on the target RF output Programmable VCO division by 1, 2, 3, 4, or 8 VCO divide-by-three with 50% duty cycle Integrated input/output RF buffer Device provides both divided and direct VCO outputs Programmable RF output power levels Low RF output comparison spurs Programmable 18-bit N-counter and 11-bit R-counter Dual modulus 7 GHz prescaler (64/65) Programmable charge pump current Flexible configuration allows connection to external VCO or PLL Bidirectional read/write three-wire serial to parallel interface Digital lock detect Digital output used as a loop filter component switch Optional adjustment of the core, divider, and charge pump current by external resistor Power supply: 3.3 V Small, RFLGA (32-pin, 5 x 5 mm) package (MSL3, 260 C per JEDEC J-STD-020) Skyworks offers lead (Pb)-free, RoHS (Restriction of Hazardous Substances) compliant packaging.
N/C
N/C
N/C
N/C
N/C
N/C
27
32
31
30
29
28
26 25 CLK 24 DATA 23 LE 22 EXT_VCON 21 EXT_VCOP 20 PLL_RES 19 REF_CLK 18 GND_REF 17 VCC_REF
VCC_VCO VCC_CAP VCO_RES OUT_BUFP OUT_BUFN VCC_OBUF DIV_CAP DIV_RES VCC_DIV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LF_CTRL
VCO_CP
CP_OUT
LD_OUT
VCC_PLL
VCC_DIG
VCTRL
N/C
S1839
Figure 1. SKY73134 Pinout - 32-Pin RFLGA (Top View)
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
CLK
VCO 1 VCO 2 VCO 3 VCO 4 Read/Write SPI
DATA LE
/1 Output Buffer /2 /3 /4 /8 N-Divider Digital Frequency Control VCO Calibration Phase Detector R-Divider Ref Buffer VCO Buffer VCO Out
OUT_BUFP OUT_BUFN
EXT_VCON EXT_VCOP
PLL Buffer VCO In
REF_CLK
Charge Pump
Lock Detect
VCTRL
CP_OUT
LD_OUT
S1838
Figure 2. SKY73134 Block Diagram
Table 1. SKY73134 Signal Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC_VCO VCC_CAP VCO_RES OUT_BUFP OUT_BUFN VCC_OBUF DIV_CAP DIV_RES VCC_DIV VCTRL VCC_PLL VCC_CP CP_OUT LF_CTRL LD_OUT VCC_DIG Name Supply for VCO External capacitor for VCO bias connected to VCC_VCO pin External 15 k resistor to set VCO bias Positive LO output Negative LO output Supply for output buffer External capacitor for the divider bias connected to the VCC_DIV pin External 60 k resistor to set the divider bias Supply for dividers VCO tuning voltage PLL supply Supply for charge pump Charge pump output Loop filter component switch control Lock detect output Supply for digital blocks Description Pin # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCC_REF GND_REF REF_CLK PLL_RES EXT_VCOP EXT_VCON LE DATA CLK N/C N/C N/C N/C N/C N/C N/C Name Description Supply for reference buffer Reference buffer ground Reference clock input External 24 k resistor for the PLL/charge pump bias Positive, external VCO input Negative, external VCO input Latch enable input for the SPI Data input for the SPI Clock input for the SPI No connection No connection No connection No connection No connection No connection No connection
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
Functional Description
The SKY73134 is comprised of seven main functional blocks: 1. N-divider 2. R-divider 3. Phase detector 4. Charge pump 5. VCO and digital frequency VCO calibration 6. VCO dividers 7. Lock detect N-Divider The N-divider consists of a 64/65 prescaler, 12-bit main counter, and 6-bit swallow counter. The 18 bit N-divider ratio is calculated as: N=PxM-S Where: P = Prescaler value M = Main counter value S = Swallow counter value The N-divider range is from P2 - P to 218, or it can vary from 4096 to 262144. For the 4 GHz VCO output, the minimum and maximum comparison frequency are defined as: FCOMP_MIN = VCO/NMAX = 4/218 15 kHz FCOMP_MAX = VCO/NMIN = 4/4096 977 kHz R-Divider The 11-bit programmable R-divider divides the reference input frequency and generates the reference input for the phase detector. The R-divider range varies from 1 to 211 (2048). Since FCOMP= FREF/R-divider for a comparison frequency of 100 kHz, the maximum reference frequency could be 204.8 MHz. Phase Detector The phase detector is an edge-controlled digital circuit. The circuit has two inputs: the reference signal (Ref) and the N-divider output. There are two digital outputs (Up and Dn) that drive the charge pump. When the input phase difference is positive, the Up output is pulled up to VDD. When the input phase difference is negative, the Dn output is pulled down to ground. This type of phase detector acts only on the positive edges of the input signals.
Charge Pump The charge pump is used to convert the logic levels of the Up and Dn pulses, carrying the phase error between the reference and the divided signal into analog quantities/current pulses. The output of the SKY73134 charge pump is programmable and varies between 0.9 mA and 5.4 mA. Additional adjustment of the charge pump current can be accomplished by changing the value of the external PLL bias resistor. VCO and Digital Frequency VCO Calibration The SKY73134 incorporates four VCOs. Each VCO covers a different frequency range between 2.7 and 6.0 GHz: VCO 1: 2.7 to 3.4 GHz VCO 2: 3.3 to 4.2 GHz VCO 3: 3.8 to 4.8 GHz VCO 4: 4.7 to 6.0 GHz The VCOs are designed to generate the LO signal with the tuning function controlled by the synthesizer. Each VCO uses a switch capacitor array and an analog varactor for digital tuning. The digital auto-tuning loop provides the proper 7-bit coarse tuning setting for the VCO switch capacitors. This sets the oscillation frequency as close to target as possible before starting fine analog tuning. When VCO auto-tuning is enabled, the PLL performs a seven-step successive approximation process to digitally tune the VCO close to the final programmed frequency. Once that is complete, analog tuning is enabled to lock the VCO to the programmed frequency. The auto-tuning loop is designed to compensate process variation so that the VCO fine tuning range can be reduced to cover temperature variation only. It significantly reduces VCO gain (Kv), which reduces the VCO phase noise. This ensures that the PLL is always locked. VCO Dividers The divider chain consists of dividers and LO drivers. Any VCO can be divided by 2, 3, 4, or 8, which improves the LO phase noise by 6 dB, 9.5 dB, 12 dB, and 18 dB, respectively. Using frequency division, the overall VCO range of the device is widened from 0.34 to 6.0 GHz. The output RF buffer has a programmable current that provides variation in the output RF level from -4 to +4 dBm. The direct non-divided VCO output can be monitored at the additional bidirectional internal/external VCO pins. The divider chain and the internal PLL can be locked by an external VCO.
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
Lock Detect The lock detect circuit is activated when the phase difference between the Up and Dn phase detector signals for a given number of comparison cycles is shorter than a fixed delay. The CMOS output is active high when the loop is locked. Bidirectional Digital Interface A three-wire Serial Programmable Interface (SPI) with read/write capability provides mode and bias control, and control of the PLL. The serial interface consists of three signals: the bus clock (CLK), latch enable (LE), and the serial, bidirectional data line (DATA). Write Mode. A write data stream consists of 25 bits: Bits[15:0] provide the 16-bit data block. Bits[20:16] provide the register address. Bit[21] is the read/write bit (0 = read, 1 = write). Bits[24:22] provide the device address (the SKY73134 is 011b). Read Mode. The read data stream is almost identical to the write data stream. Following the 5-bit register address, a "turn around" cycle is inserted so the baseband can disable its drive of the data
line and the addressed device on the bus can activate its data output driver. When the baseband addresses a device connected to the serial bus, the bus enable signal (LE) goes low half a clock cycle before the CLK signal becomes active. Data on the DATA line is clocked into the SKY73134 on the rising edge of the clock. Data from the SKY73134 to the baseband is clocked at the falling edge of the clock. The enable line goes high at the end of the data transfer. The clock becomes inactive one clock pulse after the enable signal goes high. The CLK signal is always disabled for at least one equivalent cycle between subsequent accesses. A timing diagram for the SPI read/write cycle is shown in Figure 3. Serial Bus Timing The SPI bus speed is programmable. Timing requirements for the CLK, DATA, and LE signals are provided in Table 2. A serial data input timing diagram is shown in Figure 4.
CLK DATA LE
A7 A6 A5 R/W A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6
Write
CLK DATA LE
A7 A6 A5 R/W A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6
Read
TurnAround
S348
Figure 3. Read/Write SPI Cycles
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Table 2. SPI Timing Requirements
Parameter tperiod thigh tsu thld tes(a) tes(b) tel(a) twidth tes(c) tel(b) Clock period Clock high time Data setup to clock rise Data hold from clock rise Clock rise to enable high Enable high to clock high Enable to clock rise Enable high width Clock fall to enable high Clock rise to enable low Description 25 10 5 5 10 10 10 20 0 10 Minimum Time (ns)
CLK
tperiod thigh
DATA
tsu thld tes (a) twidth
LE
tel (a) tes (c) tes (b) tel (a)
S293a
Figure 4. SPI Timing Diagram
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
PLL Control Registers (R-Divider and N-Divider) There are three digital PLL control registers that are used to store the R-divider and N-divider values: R_DIV, N_DIV1, and N_DIV2. By default, all registers are 25 bits wide. Bit[21] is the read/write bit, cleared when writing to the device. Bits[20:16] are the address bits of the registers. The 16 least significant bits (LSBs) represent the data bits. Three values are needed to calculate the three PLL dividers, R_DIV, N_DIV1 and N_DIV2: the desired frequency (FRF), the VCO divider (D), and the frequency step size (FSTEP). The VCO frequency (FVCO) has a range of 2.8 GHz to 5.6 GHz, and is defined by the product of the desired frequency (FRF) and the VCO divider, D:
FVCO FRF D
Bits[1:0] of the N_DIV2 register are the most significant bits (MSBs) of the 18-bit representation of the N number. Bits[15:0] of the N_DIV1 register are the LSBs of the 18-bit binary representation of the N number. The calculated R-divider and N-divider values are programmed into the SKY73134 using the SPI interface. Additional programming information is provided in the Skyworks document, SKY73134 Frequency Synthesizer Programming Guide, document number *** TBD ***. Example: A desired RF output frequency of 2000 MHz is required using a reference frequency of 38.4 MHz and a desired frequency step size of 100 kHz. If the VCO divider is equal to 2, the VCO frequency is 4000 MHz from Equation 1 and the comparison frequency is equal to 200 kHz from Equation 2. From Equations 3 and 4, the R and N values become: R = 192 = 11000000b N = 20000 = 100111000100000b These values would be programmed through the SPI interface. Figure 5 represents the bits of the R_DIV register with the value of R = 192. Figures 6 and 7 represent the bits of the N_DIV1 and N_DIV2 registers, respectively, with the value of N = 20000.
(1)
The VCO divider (equal to 1, 2, 3, 4, or 8) is chosen so that the product of FRF x D is within the specified VCO range. The frequency step size (FSTEP) is a user defined value. Given FSTEP and D, the comparison frequency (FCOMP) can be calculated by:
FCOMP FSTEP D
(2)
The R_DIV register stores the value of the 16-bit R-divider that produces the desired comparison frequency (FCOMP) for the RF PLL according to the following equation:
R FREF FCOMP
(3)
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY73134 are provided in Table 3. The recommended operating conditions are specified in Table 4 and electrical specifications are provided in Tables 5 through 7.
Where FREF is the reference frequency provided to the device. The N_DIV1 and N_DIV2 registers store the value of the N-divider according to the following equation:
N FVCO FREF R
(4)
24 0
23 0
22 0
21 0
20 1
19 1
18 0
17 0
16 0
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 1
6 1
5 0
4 0
3 0
2 0
1 0
0 0
3-Bit Device Address
5-Bit Register Address 1-Bit Read/Write Flag
16-Bit R-Divider Value
S1847
Figure 5. R_DIV Register Showing an R-Divider Value of 192
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
24 0
23 0
22 0
21 0
20 1
19 1
18 0
17 0
16 0
15 0
14 1
13 0
12 0
11 1
10 1
9 1
8 0
7 0
6 0
5 1
4 0
3 0
2 0
1 0
0 0
3-Bit Device Address
5-Bit Register Address 1-Bit Read/Write Flag
LSBs of 18-Bit N-Divider Value
S1849
Figure 6. N_DIV1 Register Showing an N-Divider Value of 20000 (LSBs)
24 0
23 0
22 0
21 0
20 1
19 1
18 0
17 0
16 0
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
3-Bit Device Address
5-Bit Register Address
MSBs of 18-Bit N-Divider Value
S1848
1-Bit Read/Write Flag
Figure 7. N_DIV2 Register Showing an N-Divider Value of 20000 (MSBs) Table 3. SKY73134 Absolute Maximum Ratings
Parameter Supply voltage (VCC_VCO, VCC_OBUF, VCC_DIV, VCC_PLL, VCC_CP, VCC_DIG, and VCC_REF pins) Supply current Operating case temperature Junction temperature Storage case temperature VCC Symbol Minimum Typical Maximum 3.6 Units V
ICC TC TJ TSTG -40 -40
150 +85 +150 +125
mA C C C
Notes: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Table 4. SKY73134 Recommended Operating Conditions
Parameter Supply voltage (VCC_VCO, VCC_OBUF, VCC_DIV, VCC_PLL, VCC_CP, VCC_DIG, and VCC_REF pins) Supply current Operating case temperature VCC Symbol Minimum 3.0 Typical 3.3 Maximum 3.6 Units V
ICC TC -40
120
130 +85
mA C
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
Table 5. Electrical Specifications: Reference Input and Charge Pump (Note 1) (TC = 25 C, Unless Otherwise Noted)
Parameter Reference input frequency Reference input sensitivity Comparison frequency Frequency step Charge pump current Output voltage compliance range Comparison spurs Locking time 20 kHz bandwidth, 1 ppm frequency error FCOMP FSTEP ICP Step size = 0.6 mA Symbol FREF Test Conditions Min 10 200 20 x D (Note 2) 20 0.9 0.4 -70 900 200 x D (Note 2) 200 2.7 800 x D (Note 2) 800 5.4 VDD - 0.4 -65 1 Typ Max 200 Units MHz mVp-p kHz kHz mA V dBc ms
Note 1: Performance is guaranteed only under the conditions listed in this Table. Note 2: D is the VCO divider (1, 2, 3, 4, or 8).
Table 6. SKY73134 Electrical Specifications: VCO and RF Output Characteristics (Note 1) (TC = +25 C, Unless Otherwise Noted)
Parameter VCO 1 frequency VCO 2 frequency VCO 3 frequency VCO 4 frequency VCO sensitivity VCO pushing VCO control voltage RF power
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Symbol
Test Condition
Min 2.7 3.3 3.8 4.7
Typical
Max 3.4 4.2 4.8 6.0
Units GHz GHz GHz GHz MHz/V MHz/V V dBm
KVCO
12
20 5
38 10 VDD - 0.4
VCTRL
0.4 -2 +2
+4
Table 7. SKY73134 Electrical Specifications: Phase Noise Performance (1 of 3) (Note 1) (TC = +25 C, Unless Otherwise Noted)
Parameter In-Band Phase Noise, Closed Loop Normalized in-band phase noise floor In-band phase noise floor divide-by-1 In-band phase noise floor divide-by-2 In-band phase noise floor divide-by-3 In-band phase noise floor divide-by-4 In-band phase noise floor divide-by-8 ICP = 3.6 mA, PLL bandwidth = 30 kHz ICP = 3.6 mA, PLL bandwidth = 30 kHz ICP = 3.6 mA, PLL bandwidth = 30 kHz ICP = 3.6 mA, PLL bandwidth = 30 kHz ICP = 3.6 mA, PLL bandwidth = 30 kHz ICP = 3.6 mA, PLL bandwidth = 30 kHz -211 -211 + 20 x logN + 10log(FCOMP) -217 + 20 xlogN + 10log(FCOMP) -220 + 20 xlogN + 10log(FCOMP) -223 + 20 xlogN + 10log(FCOMP) -229 + 20 xlogN + 10log(FCOMP) dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Symbol Test Condition Min Typical Max Units
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Table 7. SKY73134 Electrical Specifications: Phase Noise Performance (2 of 3) (Note 1) (TC = +25 C, Unless Otherwise Noted)
Parameter PLL Integrated Phase Noise Integrated phase noise (1 kHz to 10 MHz) PLL bandwidth = 30 kHz, RF output = 1 GHz, FSTEP = 200 kHz -43 dBc Symbol Test Condition Min Typical Max Units
VCO 1 Open Loop Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 3 MHz @ 10 MHz VCO 2 Open Loop Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 3 MHz @ 10 MHz VCO 3 Open Loop Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 3 MHz @ 10 MHz VCO 4 Open Loop Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 3 MHz @ 10 MHz VCO Divided by 2 Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz VCO Divided by 3 Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz VCO - 9.5 VCO - 9.5 VCO - 9.5 VCO - 9.5 dBc/Hz dBc/Hz dBc/Hz dBc/Hz VCO - 6 VCO - 6 VCO - 6 VCO - 6 dBc/Hz dBc/Hz dBc/Hz dBc/Hz -43 -74 -104 -128 -137 -148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -44 -76 -105 -128 -138 -148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -46 -77 -106 -128 -138 -147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -48 -79 -109 -133 -143 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
Table 7. SKY73134 Electrical Specifications: Phase Noise Performance (3 of 3) (Note 1) (TC = +25 C, Unless Otherwise Noted)
Parameter VCO Divided by 4 Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz VCO Divided by 8 Phase noise: @ 1 kHz @ 10 kHz @ 100 kHz
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Symbol
Test Condition
Min
Typical
Max
Units
VCO - 12 VCO - 12 VCO - 12 VCO - 12
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
VCO - 18 VCO - 18 VCO - 18
dBc/Hz dBc/Hz dBc/Hz
Evaluation Board Description
The SKY73134 Evaluation Board is used to test the performance of the SKY73134 frequency synthesizer. An assembly drawing for the Evaluation Board is shown in Figure 8 and the layer detail is provided in Figure 9. A schematic diagram of the SKY73134 Evaluation Board is shown in Figure 10. Circuit Design Configurations The following design considerations are general in nature and must be followed regardless of final use or configuration: 1. Paths to ground should be made as short as possible. 2. The ground pad of the SKY73134 has special electrical and thermal grounding requirements. This pad is the main thermal conduit for heat dissipation. Since the circuit board acts as the heat sink, it must shunt as much heat as possible from the device. Therefore, design the connection to the ground pad to dissipate the maximum wattage produced by the circuit board. 3. Skyworks recommends including external bypass capacitors on the VCC voltage inputs of the device. *** add'l info TBD ***
Package Dimensions
The PCB layout footprint for the SKY73134 is provided in Figure 11. Figure 12 shows the package dimensions for the 25-pin LGA and Figure 13 provides the tape and reel dimensions.
Package and Handling Information
Since the device package is sensitive to moisture absorption, it is baked and vacuum packed before shipping. Instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. Otherwise, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. THE SKY73134 is rated to Moisture Sensitivity Level 3 (MSL3) at 260 C. It can be used for lead or lead-free soldering. For additional information, refer to the Skyworks Application Note, PCB Design & SMT Assembly/Rework Guidelines for RFLGA Packages, document number 103147. Care must be taken when attaching this product, whether it is done manually or in a production solder reflow environment. Production quantities of this product are shipped in a standard tape and reel format. For packaging details, refer to the Skyworks Application Note, Tape and Reel Information - RF Modules, document number 101568.
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S1851
Figure 8. SKY73134 Evaluation Board Assembly Diagram
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
Layer 1: Top - Metal
Layer 2: Ground
Layer 3: Power Plane
Layer 4: Solid Ground Plane
S1852
Figure 9. SKY73134 Evaluation Board Layer Detail
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*** TBD ***
Figure 10. SKY73134 Evaluation Board Schematic
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
*** TBD ***
Figure 11. PCB Layout Footprint for the SKY73134 5 x 5 mm RFLGA
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
5.04
B C
18X 2.47
(2.35) (2.2) (0.15) Metal Pad, Pin 1
Pin 1 Indicator
16X 0.5 (2.35) 5.04 32x SMT Pad 0.05 M A B C 0.025 M A
14X 2.47
A
0.05 ABC 1 0.075 0.025 C 0.08 12X 0.5
A
2 0.05 Solder Mask Opening 0.05 A B C
Top View
(2X R0.05)
Side View
Bottom View
0.38 0.025 (0.04) Solder Mask to Pkg Edge 0.3 0.025 0.4 0.025
(0.37) (0.05) Pad to Pkg Edge
Detail A
SMT Pad Scale: 3X 7X This Rotation 7X Rotated 180 9X Rotated 90 CW 9X Rotated 90 CCW
All measurements are in millimeters Dimensioning and tolerancing according to ASME Y14.5M-1994
S1841
Figure 12. SKY73134 32-Pin RFLGA Package Dimensions
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
*** TBD ***
Figure 13. SKY73134 Tape and Reel Dimensions
Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com
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PRELIMINARY DATA SHEET * SKY73134 FREQUENCY SYNTHESIZER
Ordering Information
Model Name SKY73134 Frequency Synthesizer Manufacturing Part Number SKY73134-xx (Pb-free package) Evaluation Kit Part Number TW18-D170
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Skyworks Solutions, Inc. * Phone [781] 376-3000 * Fax [781] 376-3100 * sales@skyworksinc.com * www.skyworksinc.com
201199A * Skyworks Proprietary Information * Products and Product Information are Subject to Change Without Notice * December 15, 2009 17

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